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March 2007
HYS72D32300[G/H]BR-[5/6/7]-C HYS72D64300[G/H]BR-[5/6/7]-C HYS72D64320[G/H]BR-[5/6]-C HYS72D128320[G/H]BR-[6/7]-C
184-Pin Registered Double Data Rate SDRAM Module Reg DIMM DDR SDRAM
Internet Data Sheet
Rev. 1.32
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM
HYS72D32300[G/H]BR-[5/6/7]-C, HYS72D64300[G/H]BR-[5/6/7]-C, HYS72D64320[G/H]BR-[5/6]-C, HYS72D128320[G/H]BR-[6/7]-C Revision History: Rev. 1.32, 2007-03 Page All 6 All Subjects (major changes since last revision) Adapted internet edition Table updated Qimonda update
Previous Revision: Rev. 1.31, 2006-09 Previous Revision: Rev. 1.3, 2005-11
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qag_techdoc_rev400 / 3.2 QAG / 2006-07-21 03292006-Q22P-G7TH
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Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM
1
Overview
This chapter gives an overview of the 184-pin Registered Double Data Rate DDR2 SDRAM Modules with parity bit product family and describes its main characteristics.
1.1
Features
* Auto Refresh (CBR) and Self Refresh * All inputs and outputs SSTL_2 compatible * Re-drive for all input signals using register and PLL devices. * Serial Presence Detect with E2PROM * Low Profile Modules form factor: 133.35 mm x 28.58 mm x 4.00 mm / 2.64 mm and for 1GB 133.35 mm x 30.48 mm (1.2")x 4.00 mm * JEDEC standard reference layout for one rank 256 MB, 512 MB and two ranks 512 MB, 1 GB: PC 2700 and PC 3200 Registered DIMM Raw Cards A,B,C,D * Gold plated contacts
* 184-Pin Registered 8-Byte Dual-In-Line DDR SDRAM Module for "1U" PC, Workstation and Server main memory applications * One rank 32M x 72 and 64M x 72 and two ranks 64M x 72 and 128M x 72 organization * JEDEC standard Double Data Rate Synchronous DRAMs (DDR SDRAM) with a single + 2.5 V ( 0.2 V) power supply and + 2.6 V ( 0.1 V) power supply for DDR400 * Built with 256-Mbit DDR SDRAMs in P--TFBGA-60-1 packages * Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave)
TABLE 1
Performance
Part Number Speed Code Speed Grade max. Clock Frequency Component Module @CL3 @CL2.5 @CL2 -5 DDR400B PC3200-3033 -6 DDR333B PC2700-2533 166 166 133 -7 DDR266A PC2100-2033 -- 143 133 Unit -- -- MHz MHz MHz
fCK3 fCK2.5 fCK2
200 166 133
1.2
Description
devices and a PLL for the clock distribution. This reduces capacitive loading to the system bus, but adds one cycle to the SDRAM timing. A variety of decoupling capacitors are mounted on the PC board. The DIMMs feature serial presence detect based on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer.
The HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C and HYS72D64320GBR-5-C are low profile versions of the standard Registered DIMM modules suitable for 1U Server Applications. The Low Profile DIMM versions are available as 32M x 72 (256 MB), 64M x 72 (512 MB), 128M x 72 (1 GB) The memory array is designed with Double Data Rate Synchronous DRAMs for ECC applications. All control and address signals are re-driven on the DIMM using register
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Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM
TABLE 2
Ordering Information for Lead-Containing Products
Product Type PC3200 (CL = 3.0) HYS72D32300GBR-5-C HYS72D64300GBR-5-C HYS72D64320GBR-5-C PC2700 (CL = 2.5) HYS72D32300GBR-6-C HYS72D64300GBR-6-C HYS72D64320GBR-6-C HYS72D128320GBR-6-C PC2100 (CL = 2.0) HYS72D32300GBR-7-C HYS72D64300GBR-7-C HYS72D128320GBR-7-C PC2100R-20330-A0 PC2100R-20330-C0 PC2100R-20330-D0 1 Rank 256 MB Registered DIMM ECC 1 Rank 512 MB Registered DIMM ECC 2 Ranks 1 GB Registered DIMM ECC 256 Mbit (x8) 256 Mbit (x4) 256 Mbit (x4) PC2700R-25330-A0 PC2700R-25330-C0 PC2700R-25330-B0 PC2700R-25330-D0 1 Rank 256 MB Registered DIMM ECC 1 Rank 512 MB Registered DIMM ECC 2 Ranks 512 MB Registered DIMM ECC 2 Ranks 1 GB Registered DIMM ECC 256 Mbit (x8) 256 Mbit (x4) 256 Mbit (x8) 256 Mbit (x4) PC3200R-30330-A0 PC3200R-30330-C0 PC3200R-30330-B0 1 Rank 256 MB Registered DIMM ECC 1 Rank 512 MB Registered DIMM ECC 2 Ranks 512 MB Registered DIMM ECC 256 Mbit (x8) 256 Mbit (x4) 256 Mbit (x8) Compliance Code Description SDRAM Technology
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Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM
TABLE 3
Ordering Information for Lead-Free (RoHS Compliant) Products
Product Type
1)
Compliance Code2)
Description
SDRAM Technology 256 Mbit (x8) 256 Mbit (x4)
Note3)
PC3200 (CL = 3.0) HYS72D32300HBR-5-C HYS72D64300HBR-5-C HYS72D64320HBR-5-C PC2700 (CL = 2.5) HYS72D32300HBR-6-C HYS72D64300HBR-6-C HYS72D64320HBR-6-C PC2100 (CL = 2.0) HYS72D32300HBR-7-C HYS72D64300HBR-7-C PC2100R-20330-A0 PC2100R-20330-C0 1 Rank 256 MB Registered DIMM ECC 1 Rank 512 MB Registered DIMM ECC 2 Ranks 1 GB Registered DIMM ECC 256 Mbit (x8) 256 Mbit (x4) 256 Mbit (x4) PC2700R-25330-A0 PC2700R-25330-C0 PC2700R-25330-B0 1 Rank 256 MB Registered DIMM ECC 1 Rank 512 MB Registered DIMM ECC 2 Ranks 1 GB Registered DIMM ECC 256 Mbit (x8) 256 Mbit (x4) 256 Mbit (x4) PC3200R-30330-A0 PC3200R-30330-C0 PC3200R-30330-B0 1 Rank 256 MB Registered DIMM ECC 1 Rank 512 MB Registered DIMM ECC
2 Ranks 512 MB Registered DIMM ECC 256 Mbit (x8)
2 Ranks 512 MB Registered DIMM ECC 256 Mbit (x8)
HYS72D128320HBR-6-C PC2700R-25330-D0
HYS72D128320HBR-7-C PC2100R-20330-D0
1) All product types end with a place code designating the silicon-die revision. Reference information available on request. Example: HYS72D128300GBR-5-B, indicating Rev.B die are used for SDRAM components. 2) The Compliance Code is printed on the module labels and describes the speed sort (for example "PC2100R"), the latencies (for example "20330" means CAS latency of 2.0 clocks, Row-Column-Delay (RCD) latency of 3 clocks and Row Precharge latency of 3 clocks), JEDEC SPD code definition version 0, and the Raw Card used for this module. 3) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
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Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM
2
Pin Configuration
Pin # 125 29 122 27 141 118 115 I I I I NC I I NC I I I I SSTL SSTL SSTL SSTL SSTL SSTL SSTL -- SSTL SSTL SSTL LVCMOS SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL Address Bus 11:0 Clock Signal Complement Clock Clock Enable Rank 0 Clock Enable Rank 1 Note: 2-rank module Note: 1-rank module Chip Select of Rank 0 Chip Select of Rank 1 Note: 2-ranks module Note: 1-rank module Row Address Strobe Column Address Strobe Write Enable Register Reset Data Signals 2 4 6 8 94 95 Bank Address Bus 1:0 98 99 12 13 19 20 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL Data Bus 63:0 NC 167 A13 NC I -- SSTL Name A6 A7 A8 A9 A10 AP A11 A12 Pin Type I I I I I I I I Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL Address Signal 12 Note: Module based on 256 Mbit or larger dies Note: 128 Mbit based module Address Signal 13 Note: 1 Gbit based module Note: Module based on 512 Mbit or smaller dies Function Address Bus 11:0
The pin configuration of the Registered DDR SDRAM DIMM is listed by function in Table 4 (184 pins). The abbreviations used in columns Pin and Buffer Type are explained in Table 5 and Table 6 respectively. The pin numbering is depicted in Figure 1.
TABLE 4
Pin Configuration of RDIMM
Pin # 137 138 21 111 Name Pin Type Buffer Type Function
Clock Signals CK0 CK0 CKE0 CKE1 NC 157 158 S0 S1 NC 154 65 63 10 RAS CAS WE RESET
Control Signals NC NC --
Address Signals 59 52 48 43 41 130 37 32 BA0 BA1 A0 A1 A2 A3 A4 A5 I I I I I I I I
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Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM
Pin # 105 106 109 110 23 24 28 31 114 117 121 123 33 35 39 40 126 127 131 133 53 55 57 60 146 147 150 151 61 64 68 69 153 155 161 162 72 73 79 80
Name DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51
Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL
Function Data Bus 63:0
Pin # 165 166 170 171 83 84 87 88 174 175 178 179 44 45 49 51 134 135 142 144 5 14 25 36 56 67 78 86 47 97
Name DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8 DM0 DQS9
Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O I I/O
Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL
Function Data Bus 63:0
Check Bits 7:0
Data Strobes 8:0
Data Strobes 8:0
Data Mask 0 Note: x8 based module Data Strobe 9 Note: x4 based module Data Mask 1 Note: x8 based module Data Strobe 10 Note: x4 based module
107
DM1 DQS10
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Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM
Pin # 119
Name DM2 DQS11
Pin Type I I/O I I/O I I/O I I/O I I/O I I/O I I/O
Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL
Function Data Mask 2 Note: x8 based module Data Strobe 11 Note: x4 based module Data Mask 3 Note: x8 based module Data Strobe 12 Note: x4 based module Data Mask 4 Note: x8 based module Data Strobe 13 Note: x4 based module Data Mask 5 Note: x8 based module Data Strobe 14 Note: x4 based module Data Mask 6 Note: x8 based module Data Strobe 15 Note: x4 based module Data Mask 7 Note: x8 based module Data Strobe 16 Note: x4 based module Data Mask 8 Note: x8 based module Data Strobe 17 Note: x4 based module Serial Bus Clock Serial Bus Data Slave Address Select Bus 2:0
Pin #
Name
Pin Type PWR
Buffer Type --
Function I/O Driver Power Supply
129
DM3 DQS12
149
DM4 DQS13
159
DM5 DQS14
15, VDDQ 22, 30, 54, 62, 77, 96, 104, 112, 128, 136, 143, 156, 164, 172, 180 7, VDD 38, 46, 70, 85, 108, 120, 148, 168
PWR
--
Power Supply
169
DM6 DQS15
177
DM7 DQS16
140
DM8 DQS17
E2PROM 92 91 181 182 183 1 SCL SDA SA0 SA1 SA2 I I/O I I I AI PWR CMOS OD CMOS CMOS CMOS -- -- I/O Reference Voltage E2PROM Power Supply
Power Supplies
VREF 184 VDDSPD
VSS 3, 11, 18, 26, 34, 42, 50, 58, 66, 74, 81, 89, 93, 100, 116, 124, 132, 139, 145, 152, 160, 176
GND
--
Ground Plane
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Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM
Pin # 82
Name
Pin Type O NC
Buffer Type OD --
Function
TABLE 5
Abbreviations for Pin Type
Abbreviatio n I O I/O AI PWR GND NU NC Description Standard input-only pin. Digital levels. Output. Digital levels. I/O is a bidirectional input/output signal. Input. Analog levels. Power Ground Not Usable (JEDEC Standard) Not Connected (JEDEC Standard)
Other Pins
VDDID
VDD Identification
Not connected
9, NC 16, 17, 71, 75, 76, 90, 101, 102, 103, 113, 163, 173
TABLE 6
Abbreviations for Buffer Type
Abbreviatio n SSTL LV-CMOS CMOS OD Description Serial Stub Terminalted Logic (SSTL2) Low Voltage CMOS CMOS Levels Open Drain. The corresponding pin has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-OR.
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Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM
FIGURE 1
Pin Configuration 184 Pins, Reg
TABLE 7
Address Table
Density Organization Memory Ranks 1 1 2 2 SDRAMs # of SDRAMs # of row/rank/ columns bits 13 / 2 / 10 13 / 2 / 11 13 / 2 / 10 13 / 2 / 11 Refresh Period Interval
256 MB 512 MB 512 MB 1 GB
32 M x72 64 M x72 64 M x72 128 M x72
32 M x8 64 M x4 32 M x8 64 M x4
9 18 18 36
8K 8K 8K 8K
64 ms 64 ms 64 ms 64 ms
7.8 s 7.8 s 7.8 s 7.8 s
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HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM
3
3.1
Electrical Characteristics
Operating Conditions
This chapter lists the electrical characteristics.
This chapter contains the operating conditions tables.
TABLE 8
Absolute Maximum Ratings
Parameter Symbol min. Voltage on I/O pins relative to VSS Voltage on inputs relative to VSS Voltage on VDD supply relative to VSS Voltage on VDDQ supply relative to VSS Operating temperature (ambient) Storage temperature (plastic) Power dissipation (per SDRAM component) Short circuit output current Values typ. -- -- -- -- -- -- 1 50 max. Unit Note/ Test Condition
VIN, VOUT VIN VDD VDDQ TA TSTG PD IOUT
-0.5 -1 -1 -1 0 -55 -- --
VDDQ +0.5
+3.6 +3.6 +3.6 +70 +150 -- --
V V V V C C W mA
Attention: Permanent damage to the device may occur if "Absolute Maximum Ratings" are exceeded. This is a stress rating only, and functional operation should be restricted to recommended operation conditions. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability and exceeding only one of the values may cause irreversible damage to the integrated circuit.
TABLE 9
Electrical Characteristics and DC Operating Conditions
Parameter Symbol Min. Device Supply Voltage Device Supply Voltage Output Supply Voltage Output Supply Voltage E2PROM supply voltage Supply Voltage, I/O Supply Voltage Input Reference Voltage I/O Termination Voltage (System) Values Typ. 2.5 2.6 2.5 2.6 2.5 -- 0.5 x VDDQ -- Max. 2.7 2.7 2.7 2.7 3.6 0 0.51 x VDDQ V V V V V V V V
4) 5)
Unit Note1)/Test Condition
VDD VDD VDDQ VDDQ VDDSPD VSS, VSSQ VREF VTT
2.3 2.5 2.3 2.5 2.3 0 0.49 x VDDQ
fCK 166 MHz fCK > 166 MHz 2) fCK 166 MHz 3) fCK > 166 MHz 2)3)
VREF - 0.04
VREF + 0.04
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Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM
Parameter
Symbol Min.
Values Typ. -- -- -- -- -- -- Max.
Unit Note1)/Test Condition
VIH(DC) Input Low (Logic0) Voltage VIL(DC) Input Voltage Level, CK and VIN(DC)
Input High (Logic1) Voltage CK Inputs Input Differential Voltage, CK VID(DC) and CK Inputs VI-Matching Pull-up Current to Pull-down Current Input Leakage Current VIRatio
VREF + 0.15
-0.3 -0.3 0.36 0.71 -2
VDDQ + 0.3 VREF - 0.15 VDDQ + 0.3 VDDQ + 0.6
1.4 2
V V V V -- A
6) 6) 6)
6)7)
8)
II
Any input 0 V VIN VDD; All other pins not under test = 0 V
6)9)
Output Leakage Current
IOZ
-5 -- 16.2
-- -- --
5 -16.2 --
A mA mA
DQs are disabled; 0 V VOUT
Output High Current, Normal IOH Strength Driver Output Low Current, Normal Strength Driver 1) 0 C TA 70 C
2) 3) 4) 5) 6) 7) 8)
VDDQ VOUT = 1.95 V VOUT = 0.35 V
IOL
9)
DDR400 conditions apply for all clock frequencies above 166 MHz Under all conditions, VDDQ must be less than or equal to VDD. Peak to peak AC noise on VREF may not exceed 2% VREF (DC). VREF is also expected to track noise variations in VDDQ. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF. Inputs are not recognized as valid until VREF stabilizes. VID is the magnitude of the difference between the input level on CK and the input level on CK. The ratio of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the maximum difference between pull-up and pull-down drivers due to process variation. Values are shown per DDR SDRAM component
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Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM
3.2
Current Conditions
This chapter describes the Conditions.
TABLE 10
IDD Conditions
Parameter Operating Current 0 one bank; active/ precharge; DQ, DM, and DQS inputs changing once per clock cycle; address and control inputs changing once every two clock cycles. Operating Current 1 one bank; active/read/precharge; Burst Length = 4; see component data sheet. Precharge Power-Down Standby Current all banks idle; power-down mode; CKE VIL,MAX Precharge Floating Standby Current CS VIH,,MIN, all banks idle; CKE VIH,MIN; address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DQS and DM. Precharge Quiet Standby Current CS VIHMIN, all banks idle; CKE VIH,MIN; VIN = VREF for DQ, DQS and DM; address and other control inputs stable at VIH,MIN or VIL,MAX. Active Power-Down Standby Current one bank active; power-down mode; CKE VILMAX; VIN = VREF for DQ, DQS and DM. Active Standby Current one bank active; CS VIH,MIN; CKE VIH,MIN; tRC = tRAS,MAX; DQ, DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle. Operating Current Read one bank active; Burst Length = 2; reads; continuous burst; address and control inputs changing once per clock cycle; 50 % of data outputs changing on every clock edge; CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B; IOUT = 0 mA Operating Current Write one bank active; Burst Length = 2; writes; continuous burst; address and control inputs changing once per clock cycle; 50 % of data outputs changing on every clock edge; CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B Auto-Refresh Current tRC = tRFCMIN, burst refresh Self-Refresh Current CKE 0.2 V; external clock on Operating Current 7 four bank interleaving with Burst Length = 4; see component data sheet. Symbol
IDD0
IDD1 IDD2P IDD2F
IDD2Q
IDD3P IDD3N
IDD4R
IDD4W
IDD5 IDD6 IDD7
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HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM
3.3
Current Specifications
This chapter describes the Specifications.
TABLE 11
IDD Specification for HYS72D[128/64/32]3xxx[G/H]BR-5-C
HYS72D32300GBR-5-C HYS72D32300HBR--5-C HYS72D64300GBR-5-C HYS72D64300HBR-5-C HYS72D64320GBR-5-C HYS72D64320HBR-5-C Product Type Unit Note/ Test Conditions1) 2)
Organization
256 MB x72 1 Rank -5
512 MB x72 1 Rank -5 Max. 1370 1600 440 990 650 560 1080 1600 1650 2120 370 Typ. 2070 2380 730 1450 1020 890 1590 2470 2560 3190 640 Max. 2480 2800 790 1620 1200 720 1780 2800 2890 4130 700
512 MB x72 2 Ranks -5 Typ. 1780 2000 730 1450 1020 890 1590 2040 2090 2270 640 Max. 2080 2310 790 1620 1200 1020 1780 2310 2350 2830 700 mA mA mA mA mA mA mA mA mA mA mA
3) 3)4) 5) 5) 5) 5) 5) 3)4) 3) 3) 5)
Symbol
Typ. 1140 1360 390 880 540 470 950 1400 1450 1630 330 2530
3)4) 2950 4720 5500 3170 3660 mA 1) Test condition for maximum values: VDD = 2.7 V, TA = 10 C 2) Module IDD is calculated on the basis of component IDD and includes Register and PLL 3) The module IDD values are calculated from the component IDD datasheet values are: n * IDD x [component] for single bank modules (n: number of components per module bank) n * IDD x [component] + n * IDD3N [component] for two bank modules (n: number of
IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7
components per module bank) 4) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions 5) The module IDD values are calculated from the component IDD datasheet values are: n * IDD x [component] for single bank modules (n: number of components per module bank)2 * n * IDD x [component] for single two bank modules (n: number of components per module bank)
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HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM
TABLE 12
IDD Specification for HYS72D[256/128/64/32]3xxx[G/H]BR-6-C
HYS72D32300GBR-6-C HYS72D32300HBR-6-C HYS72D64300GBR-6-C HYS72D64300HBR-6-C HYS72D64320GBR-6-C HYS72D64320HBR-6-C Product Type HYS72D128320GBR-6-C HYS72D128320HBR-6-C Unit Note/ Test Conditions1) 2)
Organization
256 MB x72 1 Rank -6
512 MB x72 1 Rank -6 Max. 1190 1410 410 880 580 500 950 1410 1450 1820 370 2580 Typ. 1790 2090 650 1250 890 780 1380 2090 2180 2750 580 Max. 2110 2420 710 1400 1050 640 1540 2420 2510 3510 640
512 MB x72 2 Ranks -6 Typ. 1540 1750 650 1250 890 780 1380 1750 1790 1960 580 Max. 1780 2000 710 1400 1050 890 1540 2000 2040 2410 640
1 GB x72 2 Ranks -6 Typ. 2870 3160 1220 2200 1690 1480 2450 3160 3250 3830 1110 Max. 3290 3600 1300 2440 1980 1660 2730 3600 3690 4690 1190 mA mA mA mA mA mA mA mA mA mA mA
3) 3)4) 5) 5) 5) 5) 5) 3)4) 3) 3) 5)
Symbol
Typ. 1000 1210 370 780 480 430 840 1210 1250 1420 320 2200
3)4) 4070 4760 2740 3170 5140 5940 mA 1) Test condition for maximum values: VDD = 2.7 V, TA = 10 C 2) Module IDD is calculated on the basis of component IDD and includes Register and PLL 3) The module IDD values are calculated from the component IDD datasheet values are: n * IDD x [component] for single bank modules (n: number of components per module bank)n * IDD x [component] + n * IDD3N [component] for two bank modules (n: number of
IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7
components per module bank) 4) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions 5) The module IDD values are calculated from the component IDD datasheet values are: n * IDD x [component] for single bank modules (n: number of components per module bank)2 * n * IDD x [component] for single two bank modules (n: number of components per module bank)
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HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM
TABLE 13
IDD Specification for HYS72D[128/64/32]3xxx[G/H]BR-7-C
HYS72D32300GBR-7-C HYS72D32300HBR-7-C HYS72D64300GBR-7-C HYS72D64300HBR-7-C Product Type HYS72D128320GBR-7-C HYS72D128320HBR-7-C Unit Note/ Test Conditions1) 2)
Organization
256 MB x72 1 Rank -7
512 MB x72 1 Rank -7 Max. 1040 1250 370 760 520 450 870 1200 1250 1600 350 Typ. 1510 1890 560 1050 770 660 1200 1800 1890 2310 520 Max. 1830 2120 610 1180 910 570 1390 2030 2120 3060 580
1 GB x72 2 Ranks -7 Typ. 2410 2790 1010 1810 1440 1230 2100 2700 2790 3210 940 Max. 2870 3170 1080 2010 1690 1400 2440 3080 3170 4110 1030 mA mA mA mA mA mA mA mA mA mA mA
3) 3)4) 5) 5) 5) 5) 5) 3)4) 3) 3) 5)
Symbol
Typ. 860 1100 330 670 440 380 740 1060 1100 1210 300 1780
3)4) 2100 3240 3830 4140 4880 mA 1) Test condition for maximum values: VDD = 2.7 V, TA = 10 C 2) Module IDD is calculated on the basis of component IDD and includes Register and PLL 3) The module IDD values are calculated from the component IDD datasheet values are: n * IDD x [component] for single bank modules (n: number of components per module bank)n * IDD x [component] + n * IDD3N [component] for two bank modules (n: number of
IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7
components per module bank) 4) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions 5) The module IDD values are calculated from the component IDD datasheet values are: n * IDD x [component] for single bank modules (n: number of components per module bank)2 * n * IDD x [component] for single two bank modules (n: number of components per module bank)
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HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM
3.4
AC Characteristics
This chapter describes the AC characteristics.
TABLE 14
AC Timing - Absolute Specifications for PC3200 and PC2700 Parameter Symbol -5 DDR400B Min. DQ output access time from CK/CK CK high-level width Clock cycle time Max. +0.5 0.55 8 12 12 0.55 -6 DDR333 Min. -0.7 0.45 6 6 7.5 0.45 Max. +0.7 0.55 12 12 12 0.55 ns
2)3)4)5) 2)3)4)5)
Unit Note/ Test Condition 1)
tAC tCH tCK
-0.5 0.45 5 6 7.5
tCK
ns ns ns
CL = 3.0 2)3)4)5) CL = 2.5 2)3)4)5) CL = 2.0 2)3)4)5)
2)3)4)5) 2)3)4)5)6)
CK low-level width Auto precharge write recovery + precharge time DQ and DM input hold time input)
tCL tDAL
0.45
(tWR/tCK)+(tRP/tCK) 0.4 1.75 -0.6 0.35 -- 0.72 0.4 0.2 0.2 -- -- +0.6 -- +0.40 1.25 -- -- -- 0.45 1.75 -0.6 0.35 -- 0.75 0.45 0.2 0.2 min. (tCL, tCH) -0.7 0.75 0.8 2.2 -- -- +0.6 -- +0.40 1.25 -- -- -- -- +0.7 -- -- --
tCK tCK
ns ns ns
tDH DQ and DM input pulse width (each tDIPW
DQS output access time from CK/CK tDQSCK DQS input low (high) pulse width (write cycle)
2)3)4)5) 2)3)4)5)6)
2)3)4)5) 2)3)4)5)
tDQSL,H
tCK
ns
DQS-DQ skew (DQS and associated tDQSQ DQ signals) Write command to 1st DQS latching transition DQ and DM input setup time (write cycle)
TFBGA 2)3)4)5)
2)3)4)5)
tDQSS
tCK
ns
tDS DQS falling edge hold time from CK tDSH
DQS falling edge to CK setup time (write cycle) Clock Half Period Data-out high-impedance time from CK/CK Address and control input hold time
2)3)4)5) 2)3)4)5)
tCK tCK
ns ns ns ns ns
tDSS tHP tHZ tIH
2)3)4)5)
min. (tCL, tCH) -- -- 0.6 0.7 +0.7 -- -- --
2)3)4)5) 2)3)4)5)6)
fast slew rate
3)4)5)6)7)
slow slew rate3)4)5)6)7)
2)3)4)5)8)
Control and Addr. input pulse width (each input)
tIPW
2.2
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HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM
Parameter
Symbol
-5 DDR400B Min. Max. --
-6 DDR333 Min. 0.75 Max. --
Unit Note/ Test Condition 1)
Address and control input setup time tIS
0.6
ns
fast slew rate
3)4)5)6)7)
0.7 Data-out low-impedance time from CK/CK Mode register set command cycle time DQ/DQS output hold time Data hold skew factor Active to Autoprecharge delay Active to Precharge command Active to Active/Auto-refresh command period Active to Read or Write delay Average Periodic Refresh Interval Auto-refresh to Active/Auto-refresh command period Precharge command period Read preamble Read postamble Active bank A to Active bank B command Write preamble
-- +0.7 -- -- +0.50 -- 70E+3 -- -- 7.8 -- -- 1.1 0.60 -- -- -- 0.60 -- -- --
0.8 -0.7 2
-- +0.7 -- -- +0.50 -- 70E+3 -- -- 7.8 -- -- 1.1 0.60 -- -- -- 0.60 -- -- --
ns ns
slow slew rate
3)4)5)6)7) 2)3)4)5)6)
tLZ tMRD tQH tQHS tRAP tRAS tRC tRCD tREFI tRFC tRP tRPRE tRPST tRRD
-0.7 2
tCK
ns ns ns ns ns ns s ns ns
2)3)4)5)
tHP -tQHS
--
tHP -tQHS
--
2)3)4)5)
TFBGA 2)3)4)5)
2)3)4)5) 2)3)4)5) 2)3)4)5)
tRCD
40 55 15 -- 65 15 0.9 0.40 10 0.25 0 0.40 15 2 75
tRCD
42 60 18 -- 72 18 0.9 0.40 12 0.25 0 0.40 15 1 75
2)3)4)5) 2)3)4)5)9) 2)3)4)5)
2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5)
tCK tCK
ns
tWPRE Write preamble setup time tWPRES Write postamble tWPST Write recovery time tWR Internal write to read command delay tWTR Exit self-refresh to non-read tXSNR
command
tCK
ns
2)3)4)5) 2)3)4)5)8) 2)3)4)5)8) 2)3)4)5) 2)3)4)5) 2)3)4)5)
tCK
ns
tCK
ns
2) Input slew rate 1 V/ns for DDR400, DDR333 3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals other than CK/CK, is VREF. CK/CK slew rate are 1.0 V/ns. 4) Inputs are not recognized as valid until VREF stabilizes. 5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT. 6) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time. 7) Fast slew rate 1.0 V/ns , slow slew rate 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured between VIH(ac) and VIL(ac). 8) These parameters guarantee device timing, but they are not necessarily tested on each device. 9) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
2)3)4)5) Exit self-refresh to read command tXSRD 200 -- 200 -- tCK 1) 0 C TA 70 C; VDDQ = 2.5 V 0.2 V, VDD = +2.5 V 0.2 V (DDR333); VDDQ = 2.6 V 0.1 V, VDD = +2.6 V 0.1 V (DDR400)
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HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM
TABLE 15
AC Timing - Absolute Specifications for PC2700
Parameter Symbol -7 DDR266A Min. DQ output access time from CK/CK CK high-level width Clock cycle time CK low-level width Max. +0.75 0.55 12 12 0.55 -- -- -- +0.75 -- +0.5 1.25 -- -- -- -- +0.75 -- -- -- -- -- +0.75 -- 0.75 -- 120E+3 -- -- -- -- ns
2)3)4)5) 2)3)4)5)
Unit
Note/Test Condition 1)
tAC tCH tCK
-0.75 0.45 7.5 7.5 0.45 (tWR/tCK)+(tRP/tCK) 0.5 1.75 -0.75 0.35 -- 0.75 0.5 0.2 0.2 min. (tCL, tCH) -0.75 0.9 1.0
tCK
ns ns
CL = 2.52)3)4)5) CL = 2.02)3)4)5)
2)3)4)5) 2)3)4)5)6) 2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5)
tCL Auto precharge write recovery + precharge time tDAL DQ and DM input hold time tDH DQ and DM input pulse width (each input) tDIPW DQS output access time from CK/CK tDQSCK DQS input low (high) pulse width (write cycle) tDQSL,H DQS-DQ skew (DQS and associated DQ signals) tDQSQ Write command to 1st DQS latching transition tDQSS DQ and DM input setup time tDS DQS falling edge hold time from CK (write cycle) tDSH DQS falling edge to CK setup time (write cycle) tDSS Clock Half Period tHP Data-out high-impedance time from CK/CK tHZ Address and control input hold time tIH
tCK tCK
ns ns ns
tCK
ns
FBGA2)3)4)5)
2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5)6)
tCK
ns
tCK tCK
ns ns ns ns ns ns ns ns
fast slew rate
3)4)5)6)7)
slow slew rate
3)4)5)6)8) 2)3)4)5)8)
Control and Addr. input pulse width (each input) Address and control input setup time
tIPW tIS
2.2 0.9 1.0
fast slew rate
3)4)5)6)8)
slow slew rate
3)4)5)6)8) 2)3)4)5)6) 2)3)4)5) 2)3)4)5)
Data-out low-impedance time from CK/CK Mode register set command cycle time DQ/DQS output hold time Data hold skew factor Active to Read w/AP delay Active to Precharge command Active to Active/Auto-refresh command period Active to Read or Write delay Average Periodic Refresh Interval Auto-refresh to Active/Auto-refresh command period
tLZ tMRD tQH tQHS tRAP tRAS tRC tRCD tREFI tRFC
-0.75 2
tCK
ns ns ns ns ns ns s ns
tHP - tQHS
--
FBGA2)3)4)5)
2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5)8) 2)3)4)5)
tRCD or tRASmin
45 65 20 7.8 75
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Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM
Parameter
Symbol
-7 DDR266A Min. Max. -- 1.1 0.6 -- -- -- -- -- -- -- --
Unit
Note/Test Condition 1)
Precharge command period Read preamble Read postamble Active bank A to Active bank B command Write preamble Write preamble setup time Write postamble Write recovery time Internal write to read command delay Exit self-refresh to non-read command
2) Input slew rate 1 V/ns 3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals other than CK/CK, is VREF. CK/CK slew rate are 1.0 V/ns. 4) Inputs are not recognized as valid until stabilizes. 5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT. 6) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ). 7) Fast slew rate 1.0 V/ns , slow slew rate 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured between VIH(ac) and VIL(ac). 8) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device. 9) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. 10) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 11) In all circumstances, tXSNR can be satisfied using tXSNR = tRFC,min + 1 x tCK
Exit self-refresh to read command 1) VDDQ = 2.5 V 0.2 V, VDD = +2.5 V 0.2 V ; 0 C TA 70 C
tRP tRPRE tRPST tRRD tWPRE tWPRES tWPST tWR tWTR tXSNR tXSRD
20 0.9 0.4 15 0.25 0 0.4 15 1 75 200
ns
2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5)9) 2)3)4)5)10) 2)3)4)5) 2)3)4)5) 2)3)4)5)11) 2)3)4)5)
tCK tCK
ns
tCK
ns
tCK
ns
tCK
ns
tCK
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HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM
4
SPD Codes
This chapter lists all hexadecimal byte values stored in the EEPROM of the products described in this data sheet. SPD stands for serial presence detect. All values with XX in the table are module specific bytes which are defined during production. List of SPD Code Tables * * * * * * Table 16 "HYS72D[32/64]3x0GBR-5-C" on Page 21 Table 17 "HYS72D[32/64/128]3x0GBR-6-C" on Page 25 Table 18 "HYS72D[32/64/128]3x0GBR-7-C" on Page 29 Table 19 "HYS72D[32/64]3x0HBR-5-C" on Page 33 Table 20 "HYS72D[32/64/128]3x0HBR-6-C" on Page 37 Table 21 "HYS72D[32/64/128]3x0HBR-7-C" on Page 41
TABLE 16
HYS72D[32/64]3x0GBR-5-C
HYS72D32300GBR-5-C HYS72D64300GBR-5-C Product Type HYS72D64320GBR-5-C 512MB x72 2 Ranks (x8) PC3200R-30331 Rev. 1.0 HEX 80 08 07 0D 0A 02 48 00 04 50 50
Organization
256MB x72 1 Rank (x8)
512MB x72 1 Rank (x4) PC3200R-30331 Rev. 1.0 HEX 80 08 07 0D 0B 01 48 00 04 50 50
Label Code JEDEC SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 Description Programmed SPD Bytes in E2PROM Total number of Bytes in E2PROM Memory Type (DDR = 07h) Number of Row Addresses Number of Column Addresses Number of DIMM Ranks Data Width (LSB) Data Width (MSB) Interface Voltage Levels tCK @ CLmax (Byte 18) [ns] tAC SDRAM @ CLmax (Byte 18) [ns]
PC3200R-30331 Rev. 1.0 HEX 80 08 07 0D 0A 01 48 00 04 50 50
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HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM
HYS72D32300GBR-5-C
HYS72D64300GBR-5-C
Product Type
Organization
256MB x72 1 Rank (x8)
512MB x72 1 Rank (x4) PC3200R-30331 Rev. 1.0 HEX 02 82 04 04 01 0E 04 1C 01 02 26 C1 60 50 75 50 3C 28 3C 28 80 60 60 40 40 00 37
512MB x72 2 Ranks (x8) PC3200R-30331 Rev. 1.0 HEX 02 82 08 08 01 0E 04 1C 01 02 26 C1 60 50 75 50 3C 28 3C 28 40 60 60 40 40 00 37
Label Code JEDEC SPD Revision Byte# 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 - 40 41 Description Error Correction Support Refresh Rate Primary SDRAM Width Error Checking SDRAM Width tCCD [cycles] Burst Length Supported Number of Banks on SDRAM Device CAS Latency CS Latency Write Latency DIMM Attributes Component Attributes tCK @ CLmax -0.5 (Byte 18) [ns] tAC SDRAM @ CLmax -0.5 [ns] tCK @ CLmax -1 (Byte 18) [ns] tAC SDRAM @ CLmax -1 [ns] tRPmin [ns] tRRDmin [ns] tRCDmin [ns] tRASmin [ns] Module Density per Rank tAS, tCS [ns] tAH, tCH [ns] tDS [ns] tDH [ns] Not used tRCmin [ns]
PC3200R-30331 Rev. 1.0 HEX 02 82 08 08 01 0E 04 1C 01 02 26 C1 60 50 75 50 3C 28 3C 28 40 60 60 40 40 00 37
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HYS72D64320GBR-5-C
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM
HYS72D32300GBR-5-C
HYS72D64300GBR-5-C
Product Type
Organization
256MB x72 1 Rank (x8)
512MB x72 1 Rank (x4) PC3200R-30331 Rev. 1.0 HEX 41 28 28 50 00 01 00 10 5F 7F 7F 7F 7F 7F 51 00 00 xx 37 32 44 36 34 33 30 30 47
512MB x72 2 Ranks (x8) PC3200R-30331 Rev. 1.0 HEX 41 28 28 50 00 01 00 10 27 7F 7F 7F 7F 7F 51 00 00 xx 37 32 44 36 34 33 32 30 47
Label Code JEDEC SPD Revision Byte# 42 43 44 45 46 47 48 - 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 Description tRFCmin [ns] tCKmax [ns] tDQSQmax [ns] tQHSmax [ns] not used DIMM PCB Height Not used SPD Revision Checksum of Byte 0-62 Manufacturer's JEDEC ID Code (1) Manufacturer's JEDEC ID Code (2) Manufacturer's JEDEC ID Code (3) Manufacturer's JEDEC ID Code (4) Manufacturer's JEDEC ID Code (5) Manufacturer's JEDEC ID Code (6) Manufacturer's JEDEC ID Code (7) Manufacturer's JEDEC ID Code (8) Module Manufacturer Location Part Number, Char 1 Part Number, Char 2 Part Number, Char 3 Part Number, Char 4 Part Number, Char 5 Part Number, Char 6 Part Number, Char 7 Part Number, Char 8 Part Number, Char 9
PC3200R-30331 Rev. 1.0 HEX 41 28 28 50 00 01 00 10 26 7F 7F 7F 7F 7F 51 00 00 xx 37 32 44 33 32 33 30 30 47
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HYS72D64320GBR-5-C
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM
HYS72D32300GBR-5-C
HYS72D64300GBR-5-C
Product Type
Organization
256MB x72 1 Rank (x8)
512MB x72 1 Rank (x4) PC3200R-30331 Rev. 1.0 HEX 42 52 35 43 20 20 20 20 20 1x xx xx xx xx 00
512MB x72 2 Ranks (x8) PC3200R-30331 Rev. 1.0 HEX 42 52 35 43 20 20 20 20 20 1x xx xx xx xx 00
Label Code JEDEC SPD Revision Byte# 82 83 84 85 86 87 88 89 90 91 92 93 94 95 - 98 Description Part Number, Char 10 Part Number, Char 11 Part Number, Char 12 Part Number, Char 13 Part Number, Char 14 Part Number, Char 15 Part Number, Char 16 Part Number, Char 17 Part Number, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number
PC3200R-30331 Rev. 1.0 HEX 42 52 35 43 20 20 20 20 20 1x xx xx xx xx 00
99 - 127 Not used
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Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM
TABLE 17
HYS72D[32/64/128]3x0GBR-6-C
HYS72D32300GBR-6-C HYS72D64300GBR-6-C HYS72D64320GBR-6-C Product Type HYS72D128320GBR-6-C 1 GByte x72 PC2700R- 25330 Rev. 0.0 HEX 80 08 07 0D 0B 02 48 00 04 60 70 02 82 04 04 01 0E 04 0C 01 02 26 C1
Organization
256MB x72 1 Rank (x8)
512MB x72 1 Rank (x4) PC2700R- 25330 Rev. 0.0 HEX 80 08 07 0D 0B 01 48 00 04 60 70 02 82 04 04 01 0E 04 0C 01 02 26 C1
512MB x72
2 Ranks (x8) 2 Ranks (x4) PC2700R- 25330 Rev. 0.0 HEX 80 08 07 0D 0A 02 48 00 04 60 70 02 82 08 08 01 0E 04 0C 01 02 26 C1
Label Code JEDEC SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Description Programmed SPD Bytes in E2PROM Total number of Bytes in E2PROM Memory Type (DDR = 07h) Number of Row Addresses Number of Column Addresses Number of DIMM Ranks Data Width (LSB) Data Width (MSB) Interface Voltage Levels tCK @ CLmax (Byte 18) [ns] tAC SDRAM @ CLmax (Byte 18) [ns] Error Correction Support Refresh Rate Primary SDRAM Width Error Checking SDRAM Width tCCD [cycles] Burst Length Supported Number of Banks on SDRAM Device CAS Latency CS Latency Write Latency DIMM Attributes Component Attributes
PC2700R- 25330 Rev. 0.0 HEX 80 08 07 0D 0A 01 48 00 04 60 70 02 82 08 08 01 0E 04 0C 01 02 26 C1
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Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM
HYS72D32300GBR-6-C
HYS72D64300GBR-6-C
Organization
256MB x72 1 Rank (x8)
512MB x72 1 Rank (x4) PC2700R- 25330 Rev. 0.0 HEX 75 70 00 00 48 30 48 2A 80 75 75 45 45 00 3C 48 30 28 50 00 00 00 00 48 7F
512MB x72
HYS72D64320GBR-6-C
Product Type
1 GByte x72
2 Ranks (x8) 2 Ranks (x4) PC2700R- 25330 Rev. 0.0 HEX 75 70 00 00 48 30 48 2A 40 75 75 45 45 00 3C 48 30 28 50 00 00 00 00 10 7F PC2700R- 25330 Rev. 0.0 HEX 75 70 00 00 48 30 48 2A 80 75 75 45 45 00 3C 48 30 28 50 00 00 00 00 49 7F
Label Code JEDEC SPD Revision Byte# 23 24 25 26 27 28 29 30 31 32 33 34 35 36 - 40 41 42 43 44 45 46 47 48 - 61 62 63 64 Description tCK @ CLmax -0.5 (Byte 18) [ns] tAC SDRAM @ CLmax -0.5 [ns] tCK @ CLmax -1 (Byte 18) [ns] tAC SDRAM @ CLmax -1 [ns] tRPmin [ns] tRRDmin [ns] tRCDmin [ns] tRASmin [ns] Module Density per Rank tAS, tCS [ns] tAH, tCH [ns] tDS [ns] tDH [ns] Not used tRCmin [ns] tRFCmin [ns] tCKmax [ns] tDQSQmax [ns] tQHSmax [ns] not used DIMM PCB Height Not used SPD Revision Checksum of Byte 0-62 Manufacturer's JEDEC ID Code (1)
PC2700R- 25330 Rev. 0.0 HEX 75 70 00 00 48 30 48 2A 40 75 75 45 45 00 3C 48 30 28 50 00 00 00 00 0F 7F
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HYS72D128320GBR-6-C
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM
HYS72D32300GBR-6-C
HYS72D64300GBR-6-C
Organization
256MB x72 1 Rank (x8)
512MB x72 1 Rank (x4) PC2700R- 25330 Rev. 0.0 HEX 7F 7F 7F 7F 51 00 00 xx 37 32 44 36 34 33 30 30 47 42 52 36 43 20 20 20 20
512MB x72
HYS72D64320GBR-6-C
Product Type
1 GByte x72
2 Ranks (x8) 2 Ranks (x4) PC2700R- 25330 Rev. 0.0 HEX 7F 7F 7F 7F 51 00 00 xx 37 32 44 36 34 33 32 30 47 42 52 36 43 20 20 20 20 PC2700R- 25330 Rev. 0.0 HEX 7F 7F 7F 7F 51 00 00 xx 37 32 44 31 32 38 33 32 30 47 42 52 36 43 20 20 20
Label Code JEDEC SPD Revision Byte# 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 Description Manufacturer's JEDEC ID Code (2) Manufacturer's JEDEC ID Code (3) Manufacturer's JEDEC ID Code (4) Manufacturer's JEDEC ID Code (5) Manufacturer's JEDEC ID Code (6) Manufacturer's JEDEC ID Code (7) Manufacturer's JEDEC ID Code (8) Module Manufacturer Location Part Number, Char 1 Part Number, Char 2 Part Number, Char 3 Part Number, Char 4 Part Number, Char 5 Part Number, Char 6 Part Number, Char 7 Part Number, Char 8 Part Number, Char 9 Part Number, Char 10 Part Number, Char 11 Part Number, Char 12 Part Number, Char 13 Part Number, Char 14 Part Number, Char 15 Part Number, Char 16 Part Number, Char 17
PC2700R- 25330 Rev. 0.0 HEX 7F 7F 7F 7F 51 00 00 xx 37 32 44 33 32 33 30 30 47 42 52 36 43 20 20 20 20
Rev. 1.32, 2007-03 03292006-Q22P-G7TH
27
HYS72D128320GBR-6-C
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM
HYS72D32300GBR-6-C
HYS72D64300GBR-6-C
Organization
256MB x72 1 Rank (x8)
512MB x72 1 Rank (x4) PC2700R- 25330 Rev. 0.0 HEX 20 1x xx xx xx xx 00
512MB x72
HYS72D64320GBR-6-C
Product Type
1 GByte x72
2 Ranks (x8) 2 Ranks (x4) PC2700R- 25330 Rev. 0.0 HEX 20 1x xx xx xx xx 00 PC2700R- 25330 Rev. 0.0 HEX 20 1x xx xx xx xx 00
Label Code JEDEC SPD Revision Byte# 90 91 92 93 94 95 - 98 Description Part Number, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number
PC2700R- 25330 Rev. 0.0 HEX 20 1x xx xx xx xx 00
99 - 127 Not used
Rev. 1.32, 2007-03 03292006-Q22P-G7TH
28
HYS72D128320GBR-6-C
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM
TABLE 18
HYS72D[32/64/128]3x0GBR-7-C
HYS72D32300GBR-7-C HYS72D64300GBR-7-C Product Type HYS72D128320GBR-7-C 1 GByte x72 2 Ranks (x4) PC2100R-20330 Rev. 0.0 HEX 80 08 07 0D 0B 02 48 00 04 70 75 02 82 04 04 01 0E 04 0C 01 02 26 C1 75
Organization
256MB x72 1 Rank (x8)
512MB x72 1 Rank (x4) PC2100R-20331 Rev. 1.0 HEX 80 08 07 0D 0B 01 48 00 04 70 75 02 82 04 04 01 0E 04 0C 01 02 26 C1 75
Label Code JEDEC SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Description Programmed SPD Bytes in E2PROM Total number of Bytes in E2PROM Memory Type (DDR = 07h) Number of Row Addresses Number of Column Addresses Number of DIMM Ranks Data Width (LSB) Data Width (MSB) Interface Voltage Levels tCK @ CLmax (Byte 18) [ns] tAC SDRAM @ CLmax (Byte 18) [ns] Error Correction Support Refresh Rate Primary SDRAM Width Error Checking SDRAM Width tCCD [cycles] Burst Length Supported Number of Banks on SDRAM Device CAS Latency CS Latency Write Latency DIMM Attributes Component Attributes tCK @ CLmax -0.5 (Byte 18) [ns]
PC2100R-20330 Rev. 0.0 HEX 80 08 07 0D 0A 01 48 00 04 70 75 02 82 08 08 01 0E 04 0C 01 02 26 C1 75
Rev. 1.32, 2007-03 03292006-Q22P-G7TH
29
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM
HYS72D32300GBR-7-C
Organization
256MB x72 1 Rank (x8)
512MB x72 1 Rank (x4) PC2100R-20331 Rev. 1.0 HEX 75 00 00 50 3C 50 2D 80 90 90 50 50 00 41 4B 30 32 75 00 00 00 10 14 7F 7F 7F
HYS72D64300GBR-7-C
Product Type
1 GByte x72 2 Ranks (x4) PC2100R-20330 Rev. 0.0 HEX 75 00 00 50 3C 50 2D 80 90 90 50 50 00 41 4B 30 32 75 00 00 00 00 05 7F 7F 7F
Label Code JEDEC SPD Revision Byte# 24 25 26 27 28 29 30 31 32 33 34 35 36 - 40 41 42 43 44 45 46 47 48 - 61 62 63 64 65 66 Description tAC SDRAM @ CLmax -0.5 [ns] tCK @ CLmax -1 (Byte 18) [ns] tAC SDRAM @ CLmax -1 [ns] tRPmin [ns] tRRDmin [ns] tRCDmin [ns] tRASmin [ns] Module Density per Rank tAS, tCS [ns] tAH, tCH [ns] tDS [ns] tDH [ns] Not used tRCmin [ns] tRFCmin [ns] tCKmax [ns] tDQSQmax [ns] tQHSmax [ns] not used DIMM PCB Height Not used SPD Revision Checksum of Byte 0-62 Manufacturer's JEDEC ID Code (1) Manufacturer's JEDEC ID Code (2) Manufacturer's JEDEC ID Code (3)
PC2100R-20330 Rev. 0.0 HEX 75 00 00 50 3C 50 2D 40 90 90 50 50 00 41 4B 30 32 75 00 00 00 00 CB 7F 7F 7F
Rev. 1.32, 2007-03 03292006-Q22P-G7TH
30
HYS72D128320GBR-7-C
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM
HYS72D32300GBR-7-C
Organization
256MB x72 1 Rank (x8)
512MB x72 1 Rank (x4) PC2100R-20331 Rev. 1.0 HEX 7F 7F 51 00 00 xx 37 32 44 36 34 33 30 30 47 42 52 37 43 20 20 20 20 20 0x xx
HYS72D64300GBR-7-C
Product Type
1 GByte x72 2 Ranks (x4) PC2100R-20330 Rev. 0.0 HEX 7F 7F 51 00 00 xx 37 32 44 31 32 38 33 32 30 47 42 52 37 43 20 20 20 20 1x xx
Label Code JEDEC SPD Revision Byte# 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 Description Manufacturer's JEDEC ID Code (4) Manufacturer's JEDEC ID Code (5) Manufacturer's JEDEC ID Code (6) Manufacturer's JEDEC ID Code (7) Manufacturer's JEDEC ID Code (8) Module Manufacturer Location Part Number, Char 1 Part Number, Char 2 Part Number, Char 3 Part Number, Char 4 Part Number, Char 5 Part Number, Char 6 Part Number, Char 7 Part Number, Char 8 Part Number, Char 9 Part Number, Char 10 Part Number, Char 11 Part Number, Char 12 Part Number, Char 13 Part Number, Char 14 Part Number, Char 15 Part Number, Char 16 Part Number, Char 17 Part Number, Char 18 Module Revision Code Test Program Revision Code
PC2100R-20330 Rev. 0.0 HEX 7F 7F 51 00 00 xx 37 32 44 33 32 33 30 30 47 42 52 37 43 20 20 20 20 20 1x xx
Rev. 1.32, 2007-03 03292006-Q22P-G7TH
31
HYS72D128320GBR-7-C
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM
HYS72D32300GBR-7-C
Organization
256MB x72 1 Rank (x8)
512MB x72 1 Rank (x4) PC2100R-20331 Rev. 1.0 HEX xx xx xx 00
HYS72D64300GBR-7-C
Product Type
1 GByte x72 2 Ranks (x4) PC2100R-20330 Rev. 0.0 HEX xx xx xx 00
Label Code JEDEC SPD Revision Byte# 93 94 95 - 98 Description Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number
PC2100R-20330 Rev. 0.0 HEX xx xx xx 00
99 - 127 Not used
Rev. 1.32, 2007-03 03292006-Q22P-G7TH
32
HYS72D128320GBR-7-C
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM
TABLE 19
HYS72D[32/64]3x0HBR-5-C
HYS72D32300HBR-5-C HYS72D64300HBR-5-C Product Type HYS72D64320HBR-5-C 512MB x72 2 Ranks (x8) PC3200R-30331 Rev. 1.0 HEX 80 08 07 0D 0A 02 48 00 04 50 50 02 82 08 08 01 0E 04 1C 01 02 26 C1 60
Organization
256MB x72 1 Rank (x8)
512MB x72 1 Rank (x4) PC3200R-30331 Rev. 1.0 HEX 80 08 07 0D 0B 01 48 00 04 50 50 02 82 04 04 01 0E 04 1C 01 02 26 C1 60
Label Code JEDEC SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Description Programmed SPD Bytes in E2PROM Total number of Bytes in E2PROM Memory Type (DDR = 07h) Number of Row Addresses Number of Column Addresses Number of DIMM Ranks Data Width (LSB) Data Width (MSB) Interface Voltage Levels tCK @ CLmax (Byte 18) [ns] tAC SDRAM @ CLmax (Byte 18) [ns] Error Correction Support Refresh Rate Primary SDRAM Width Error Checking SDRAM Width tCCD [cycles] Burst Length Supported Number of Banks on SDRAM Device CAS Latency CS Latency Write Latency DIMM Attributes Component Attributes tCK @ CLmax -0.5 (Byte 18) [ns]
PC3200R-30331 Rev. 1.0 HEX 80 08 07 0D 0A 01 48 00 04 50 50 02 82 08 08 01 0E 04 1C 01 02 26 C1 60
Rev. 1.32, 2007-03 03292006-Q22P-G7TH
33
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM
HYS72D32300HBR-5-C
HYS72D64300HBR-5-C
Product Type
Organization
256MB x72 1 Rank (x8)
512MB x72 1 Rank (x4) PC3200R-30331 Rev. 1.0 HEX 50 75 50 3C 28 3C 28 80 60 60 40 40 00 37 41 28 28 50 00 01 00 10 5F 7F 7F 7F 7F
512MB x72 2 Ranks (x8) PC3200R-30331 Rev. 1.0 HEX 50 75 50 3C 28 3C 28 40 60 60 40 40 00 37 41 28 28 50 00 01 00 10 27 7F 7F 7F 7F
Label Code JEDEC SPD Revision Byte# 24 25 26 27 28 29 30 31 32 33 34 35 36 - 40 41 42 43 44 45 46 47 48 - 61 62 63 64 65 66 67 Description tAC SDRAM @ CLmax -0.5 [ns] tCK @ CLmax -1 (Byte 18) [ns] tAC SDRAM @ CLmax -1 [ns] tRPmin [ns] tRRDmin [ns] tRCDmin [ns] tRASmin [ns] Module Density per Rank tAS, tCS [ns] tAH, tCH [ns] tDS [ns] tDH [ns] Not used tRCmin [ns] tRFCmin [ns] tCKmax [ns] tDQSQmax [ns] tQHSmax [ns] not used DIMM PCB Height Not used SPD Revision Checksum of Byte 0-62 Manufacturer's JEDEC ID Code (1) Manufacturer's JEDEC ID Code (2) Manufacturer's JEDEC ID Code (3) Manufacturer's JEDEC ID Code (4)
PC3200R-30331 Rev. 1.0 HEX 50 75 50 3C 28 3C 28 40 60 60 40 40 00 37 41 28 28 50 00 01 00 10 26 7F 7F 7F 7F
Rev. 1.32, 2007-03 03292006-Q22P-G7TH
34
HYS72D64320HBR-5-C
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM
HYS72D32300HBR-5-C
HYS72D64300HBR-5-C
Product Type
Organization
256MB x72 1 Rank (x8)
512MB x72 1 Rank (x4) PC3200R-30331 Rev. 1.0 HEX 7F 51 00 00 xx 37 32 44 36 34 33 30 30 48 42 52 35 43 20 20 20 20 20 1x xx xx xx
512MB x72 2 Ranks (x8) PC3200R-30331 Rev. 1.0 HEX 7F 51 00 00 xx 37 32 44 36 34 33 32 30 48 42 52 35 43 20 20 20 20 20 1x xx xx xx
Label Code JEDEC SPD Revision Byte# 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 Description Manufacturer's JEDEC ID Code (5) Manufacturer's JEDEC ID Code (6) Manufacturer's JEDEC ID Code (7) Manufacturer's JEDEC ID Code (8) Module Manufacturer Location Part Number, Char 1 Part Number, Char 2 Part Number, Char 3 Part Number, Char 4 Part Number, Char 5 Part Number, Char 6 Part Number, Char 7 Part Number, Char 8 Part Number, Char 9 Part Number, Char 10 Part Number, Char 11 Part Number, Char 12 Part Number, Char 13 Part Number, Char 14 Part Number, Char 15 Part Number, Char 16 Part Number, Char 17 Part Number, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week
PC3200R-30331 Rev. 1.0 HEX 7F 51 00 00 xx 37 32 44 33 32 33 30 30 48 42 52 35 43 20 20 20 20 20 1x xx xx xx
Rev. 1.32, 2007-03 03292006-Q22P-G7TH
35
HYS72D64320HBR-5-C
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM
HYS72D32300HBR-5-C
HYS72D64300HBR-5-C
Product Type
Organization
256MB x72 1 Rank (x8)
512MB x72 1 Rank (x4) PC3200R-30331 Rev. 1.0 HEX xx 00
512MB x72 2 Ranks (x8) PC3200R-30331 Rev. 1.0 HEX xx 00
Label Code JEDEC SPD Revision Byte# 95 - 98 Description Module Serial Number
PC3200R-30331 Rev. 1.0 HEX xx 00
99 - 127 Not used
Rev. 1.32, 2007-03 03292006-Q22P-G7TH
36
HYS72D64320HBR-5-C
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM
TABLE 20
HYS72D[32/64/128]3x0HBR-6-C
HYS72D32300HBR-6-C HYS72D64300HBR-6-C HYS72D64320HBR-6-C Product Type HYS72D128320HBR-6-C 1 GByte x72 PC2700R- 25330 Rev. 0.0 HEX 80 08 07 0D 0B 02 48 00 04 60 70 02 82 04 04 01 0E 04 0C 01 02 26 C1
Organization
256MB x72 1 Rank (x8)
512MB x72 1 Rank (x4) PC2700R- 25330 Rev. 0.0 HEX 80 08 07 0D 0B 01 48 00 04 60 70 02 82 04 04 01 0E 04 0C 01 02 26 C1
512MB x72
2 Ranks (x8) 2 Ranks (x4) PC2700R- 25330 Rev. 0.0 HEX 80 08 07 0D 0A 02 48 00 04 60 70 02 82 08 08 01 0E 04 0C 01 02 26 C1
Label Code JEDEC SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Description Programmed SPD Bytes in E2PROM Total number of Bytes in E2PROM Memory Type (DDR = 07h) Number of Row Addresses Number of Column Addresses Number of DIMM Ranks Data Width (LSB) Data Width (MSB) Interface Voltage Levels tCK @ CLmax (Byte 18) [ns] tAC SDRAM @ CLmax (Byte 18) [ns] Error Correction Support Refresh Rate Primary SDRAM Width Error Checking SDRAM Width tCCD [cycles] Burst Length Supported Number of Banks on SDRAM Device CAS Latency CS Latency Write Latency DIMM Attributes Component Attributes
PC2700R- 25330 Rev. 0.0 HEX 80 08 07 0D 0A 01 48 00 04 60 70 02 82 08 08 01 0E 04 0C 01 02 26 C1
Rev. 1.32, 2007-03 03292006-Q22P-G7TH
37
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM
HYS72D32300HBR-6-C
HYS72D64300HBR-6-C
Organization
256MB x72 1 Rank (x8)
512MB x72 1 Rank (x4) PC2700R- 25330 Rev. 0.0 HEX 75 70 00 00 48 30 48 2A 80 75 75 45 45 00 3C 48 30 28 50 00 00 00 00 48 7F 7F
512MB x72
HYS72D64320HBR-6-C
Product Type
1 GByte x72
2 Ranks (x8) 2 Ranks (x4) PC2700R- 25330 Rev. 0.0 HEX 75 70 00 00 48 30 48 2A 40 75 75 45 45 00 3C 48 30 28 50 00 00 00 00 10 7F 7F PC2700R- 25330 Rev. 0.0 HEX 75 70 00 00 48 30 48 2A 80 75 75 45 45 00 3C 48 30 28 50 00 00 00 00 49 7F 7F
Label Code JEDEC SPD Revision Byte# 23 24 25 26 27 28 29 30 31 32 33 34 35 36 - 40 41 42 43 44 45 46 47 48 - 61 62 63 64 65 Description tCK @ CLmax -0.5 (Byte 18) [ns] tAC SDRAM @ CLmax -0.5 [ns] tCK @ CLmax -1 (Byte 18) [ns] tAC SDRAM @ CLmax -1 [ns] tRPmin [ns] tRRDmin [ns] tRCDmin [ns] tRASmin [ns] Module Density per Rank tAS, tCS [ns] tAH, tCH [ns] tDS [ns] tDH [ns] Not used tRCmin [ns] tRFCmin [ns] tCKmax [ns] tDQSQmax [ns] tQHSmax [ns] not used DIMM PCB Height Not used SPD Revision Checksum of Byte 0-62 Manufacturer's JEDEC ID Code (1) Manufacturer's JEDEC ID Code (2)
PC2700R- 25330 Rev. 0.0 HEX 75 70 00 00 48 30 48 2A 40 75 75 45 45 00 3C 48 30 28 50 00 00 00 00 0F 7F 7F
Rev. 1.32, 2007-03 03292006-Q22P-G7TH
38
HYS72D128320HBR-6-C
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM
HYS72D32300HBR-6-C
HYS72D64300HBR-6-C
Organization
256MB x72 1 Rank (x8)
512MB x72 1 Rank (x4) PC2700R- 25330 Rev. 0.0 HEX 7F 7F 7F 51 00 00 xx 37 32 44 36 34 33 30 30 48 42 52 36 43 20 20 20 20 20 1x
512MB x72
HYS72D64320HBR-6-C
Product Type
1 GByte x72
2 Ranks (x8) 2 Ranks (x4) PC2700R- 25330 Rev. 0.0 HEX 7F 7F 7F 51 00 00 xx 37 32 44 36 34 33 32 30 48 42 52 36 43 20 20 20 20 20 1x PC2700R- 25330 Rev. 0.0 HEX 7F 7F 7F 51 00 00 xx 37 32 44 31 32 38 33 32 30 48 42 52 36 43 20 20 20 20 1x
Label Code JEDEC SPD Revision Byte# 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 Description Manufacturer's JEDEC ID Code (3) Manufacturer's JEDEC ID Code (4) Manufacturer's JEDEC ID Code (5) Manufacturer's JEDEC ID Code (6) Manufacturer's JEDEC ID Code (7) Manufacturer's JEDEC ID Code (8) Module Manufacturer Location Part Number, Char 1 Part Number, Char 2 Part Number, Char 3 Part Number, Char 4 Part Number, Char 5 Part Number, Char 6 Part Number, Char 7 Part Number, Char 8 Part Number, Char 9 Part Number, Char 10 Part Number, Char 11 Part Number, Char 12 Part Number, Char 13 Part Number, Char 14 Part Number, Char 15 Part Number, Char 16 Part Number, Char 17 Part Number, Char 18 Module Revision Code
PC2700R- 25330 Rev. 0.0 HEX 7F 7F 7F 51 00 00 xx 37 32 44 33 32 33 30 30 48 42 52 36 43 20 20 20 20 20 1x
Rev. 1.32, 2007-03 03292006-Q22P-G7TH
39
HYS72D128320HBR-6-C
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM
HYS72D32300HBR-6-C
HYS72D64300HBR-6-C
Organization
256MB x72 1 Rank (x8)
512MB x72 1 Rank (x4) PC2700R- 25330 Rev. 0.0 HEX xx xx xx xx 00
512MB x72
HYS72D64320HBR-6-C
Product Type
1 GByte x72
2 Ranks (x8) 2 Ranks (x4) PC2700R- 25330 Rev. 0.0 HEX xx xx xx xx 00 PC2700R- 25330 Rev. 0.0 HEX xx xx xx xx 00
Label Code JEDEC SPD Revision Byte# 92 93 94 95 - 98 Description Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number
PC2700R- 25330 Rev. 0.0 HEX xx xx xx xx 00
99 - 127 Not used
Rev. 1.32, 2007-03 03292006-Q22P-G7TH
40
HYS72D128320HBR-6-C
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM
TABLE 21
HYS72D[32/64/128]3x0HBR-7-C
HYS72D32300HBR-7-C HYS72D64300HBR-7-C Product Type HYS72D128320HBR-7-C 1 GByte x72 2 Ranks (x4) PC2100R-20330 Rev. 0.0 HEX 80 08 07 0D 0B 02 48 00 04 70 75 02 82 04 04 01 0E 04 0C 01 02 26 C1 75
Organization
256MB x72 1 Rank (x8)
512MB x72 1 Rank (x4) PC2100R-20331 Rev. 1.0 HEX 80 08 07 0D 0B 01 48 00 04 70 75 02 82 04 04 01 0E 04 0C 01 02 26 C1 75
Label Code JEDEC SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Description Programmed SPD Bytes in E2PROM Total number of Bytes in E2PROM Memory Type (DDR = 07h) Number of Row Addresses Number of Column Addresses Number of DIMM Ranks Data Width (LSB) Data Width (MSB) Interface Voltage Levels tCK @ CLmax (Byte 18) [ns] tAC SDRAM @ CLmax (Byte 18) [ns] Error Correction Support Refresh Rate Primary SDRAM Width Error Checking SDRAM Width tCCD [cycles] Burst Length Supported Number of Banks on SDRAM Device CAS Latency CS Latency Write Latency DIMM Attributes Component Attributes tCK @ CLmax -0.5 (Byte 18) [ns]
PC2100R-20330 Rev. 0.0 HEX 80 08 07 0D 0A 01 48 00 04 70 75 02 82 08 08 01 0E 04 0C 01 02 26 C1 75
Rev. 1.32, 2007-03 03292006-Q22P-G7TH
41
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM
HYS72D32300HBR-7-C
Organization
256MB x72 1 Rank (x8)
512MB x72 1 Rank (x4) PC2100R-20331 Rev. 1.0 HEX 75 00 00 50 3C 50 2D 80 90 90 50 50 00 41 4B 30 32 75 00 00 00 10 14 7F 7F 7F
HYS72D64300HBR-7-C
Product Type
1 GByte x72 2 Ranks (x4) PC2100R-20330 Rev. 0.0 HEX 75 00 00 50 3C 50 2D 80 90 90 50 50 00 41 4B 30 32 75 00 00 00 00 05 7F 7F 7F
Label Code JEDEC SPD Revision Byte# 24 25 26 27 28 29 30 31 32 33 34 35 36 - 40 41 42 43 44 45 46 47 48 - 61 62 63 64 65 66 Description tAC SDRAM @ CLmax -0.5 [ns] tCK @ CLmax -1 (Byte 18) [ns] tAC SDRAM @ CLmax -1 [ns] tRPmin [ns] tRRDmin [ns] tRCDmin [ns] tRASmin [ns] Module Density per Rank tAS, tCS [ns] tAH, tCH [ns] tDS [ns] tDH [ns] Not used tRCmin [ns] tRFCmin [ns] tCKmax [ns] tDQSQmax [ns] tQHSmax [ns] not used DIMM PCB Height Not used SPD Revision Checksum of Byte 0-62 Manufacturer's JEDEC ID Code (1) Manufacturer's JEDEC ID Code (2) Manufacturer's JEDEC ID Code (3)
PC2100R-20330 Rev. 0.0 HEX 75 00 00 50 3C 50 2D 40 90 90 50 50 00 41 4B 30 32 75 00 00 00 00 CB 7F 7F 7F
Rev. 1.32, 2007-03 03292006-Q22P-G7TH
42
HYS72D128320HBR-7-C
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM
HYS72D32300HBR-7-C
Organization
256MB x72 1 Rank (x8)
512MB x72 1 Rank (x4) PC2100R-20331 Rev. 1.0 HEX 7F 7F 51 00 00 xx 37 32 44 36 34 33 30 30 48 42 52 37 43 20 20 20 20 20 0x xx
HYS72D64300HBR-7-C
Product Type
1 GByte x72 2 Ranks (x4) PC2100R-20330 Rev. 0.0 HEX 7F 7F 51 00 00 xx 37 32 44 31 32 38 33 32 30 48 42 52 37 43 20 20 20 20 1x xx
Label Code JEDEC SPD Revision Byte# 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 Description Manufacturer's JEDEC ID Code (4) Manufacturer's JEDEC ID Code (5) Manufacturer's JEDEC ID Code (6) Manufacturer's JEDEC ID Code (7) Manufacturer's JEDEC ID Code (8) Module Manufacturer Location Part Number, Char 1 Part Number, Char 2 Part Number, Char 3 Part Number, Char 4 Part Number, Char 5 Part Number, Char 6 Part Number, Char 7 Part Number, Char 8 Part Number, Char 9 Part Number, Char 10 Part Number, Char 11 Part Number, Char 12 Part Number, Char 13 Part Number, Char 14 Part Number, Char 15 Part Number, Char 16 Part Number, Char 17 Part Number, Char 18 Module Revision Code Test Program Revision Code
PC2100R-20330 Rev. 0.0 HEX 7F 7F 51 00 00 xx 37 32 44 33 32 33 30 30 48 42 52 37 43 20 20 20 20 20 1x xx
Rev. 1.32, 2007-03 03292006-Q22P-G7TH
43
HYS72D128320HBR-7-C
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM
HYS72D32300HBR-7-C
Organization
256MB x72 1 Rank (x8)
512MB x72 1 Rank (x4) PC2100R-20331 Rev. 1.0 HEX xx xx xx 00
HYS72D64300HBR-7-C
Product Type
1 GByte x72 2 Ranks (x4) PC2100R-20330 Rev. 0.0 HEX xx xx xx 00
Label Code JEDEC SPD Revision Byte# 93 94 95 - 98 Description Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number
PC2100R-20330 Rev. 0.0 HEX xx xx xx 00
99 - 127 Not used
Rev. 1.32, 2007-03 03292006-Q22P-G7TH
44
HYS72D128320HBR-7-C
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM
5
5.1
Package Outlines
Raw Card A
This chapter contains the package outlines of the products.
Package Outlines - Raw Card A HYS72D32300[G/H]BR-[5/6/7]-C (1 Rank x 8)
0.1 A B C
133.35 128.95 2.64 MAX. A 0.15 A B C
FIGURE 2
4 0.1
1 2.5 0.1
o0.1 A B C
6.62 2.175 6.35
92
28.58 0.13
B 0.4 1.27 0.1 49.53 95 x 1.27 = 120.65 C 64.77 1.8 0.1 93 0.1 A B C 184
3.8 0.13
10
3 MIN.
Detail of contacts
0.2
1.27
1 0.05
2.5 0.2
0.1 A B C
Burr max. 0.4 allowed
Rev. 1.32, 2007-03 03292006-Q22P-G7TH
45
17.8
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM
5.2
Raw Card B
Package Outlines - Raw Card B HYS72D64320GBR-[5/6]-C (2 Ranks x8)
0.1 A B C
FIGURE 3
133.35 128.95
0.15 A B C 4 MAX.
A
4 0.1 28.58 0.13
1 2.5 0.1
o0.1 A B C
6.62 2.175 6.35
92
BC 0.4 1.27 0.1
64.77 95 x 1.27 = 120.65
49.53
3.8 0.13
1.8 0.1 93
0.1 A B C 184
10 17.8
3 MIN.
Detail of contacts
0.2
1.27
1 0.05
2.5 0.2
0.1 A B C
Burr max. 0.4 allowed
Rev. 1.32, 2007-03 03292006-Q22P-G7TH
46
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM
5.3
Raw Card C
Package Outlines - Raw Card C HYS72D64300[G/H]BR-[5/6/7]-C (1 Rank x 4)
FIGURE 4
Rev. 1.32, 2007-03 03292006-Q22P-G7TH
47
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM
5.4
Raw Card D
Package Outlines - Raw Card D HYS72D128320[G/H]BR-[6/7]-C (2 Ranks x4)
0.1 A B C
133.35 128.95 4 MAX. A 0.15 A B C
FIGURE 5
4 0.1
1 2.5 0.1
o0.1 A B C
6.62 2.175 6.35
92
30.48 0.13
B 0.4 1.27 0.1 49.53 95 x 1.27 = 120.65 C 64.77 1.8 0.1 93 0.1 A B C 184
3.8 0.13
10
3 MIN.
Detail of contacts
0.2
1.27
1 0.05
2.5 0.2
0.1 A B C
Burr max. 0.4 allowed
Rev. 1.32, 2007-03 03292006-Q22P-G7TH
48
17.8
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR-[5/6/7]-C Registered Double Data Rate SDRAM
Table of Contents
1 1.1 1.2 2 3 3.1 3.2 3.3 3.4 4 5 5.1 5.2 5.3 5.4 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Raw Card A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Raw Card B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Raw Card C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Raw Card D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 11 13 14 17 45 45 46 47 48
SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Rev. 1.32, 2007-03 03292006-Q22P-G7TH
49
Internet Data Sheet
Edition 2007-03 Published by Qimonda AG Gustav-Heinemann-Ring 212 D-81739 Munchen, Germany (c) Qimonda AG 2007. All Rights Reserved. Legal Disclaimer The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics ("Beschaffenheitsgarantie"). With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office. Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Qimonda Office. Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. www.qimonda.com

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